1. Field
Example embodiments relate to phase splitters. Also, example embodiments relate to phase splitters used in memory integrated circuits operating in synchronization with a clock signal.
2. Description of Related Art
A phase splitter receives an external clock signal and splits the clock signal to generate two clock signals having a phase difference of 180° between them. The phase splitter is generally used in a memory integrated circuit operating in synchronization with a clock signal, for example, a synchronous dynamic random access memory (SDRAM).
FIG. 1 is a circuit diagram of a conventional phase splitter 101. Referring to FIG. 1, the conventional phase splitter 101 receives an external clock signal CLK and generates a first internal clock signal CLKB having a phase difference of 180° with the external clock signal CLK and a second internal clock signal CLK1 having the same phase as the external clock signal CLK.
The first internal clock signal CLKB is output through a first path X on which three inverters 111, 112, and 113, connected in series, are arranged. The first internal clock signal CLKB has a phase difference of 180° with the external clock signal CLK because the first path X has an odd number of inverters 111, 112, and 113.
The second internal clock signal CLK1 is output through a second path Y on which two inverters 121 and 122, connected in series, are arranged. The second internal clock signal CLK1 has the same phase as the external clock signal CLK because the second path Y has an even number of inverters 121 and 122. Accordingly, a phase difference between the first internal clock signal CLKB and the second internal clock signal CLK1 is 180°.
However, the generation of the second internal clock signal CLK1 precedes generation of the first internal clock signal CLKB because the number of inverters on the first path X is greater than the number of inverters on the second path Y by one inverter. That is, a delay of the first internal clock signal CLKB output through the first path X is longer than a delay of the second internal clock signal CLK1 output through the second path Y. This delay difference generates a skew between the first internal clock signal CLKB and the second internal clock signal CLK1. This skew may become more severe due to variations in process, voltage, and/or temperature (PVT).
FIG. 2 illustrates a falling skew, between the first internal clock signal CLKB and the second internal clock signal CLK1 output from the conventional phase splitter 101 illustrated in FIG. 1, in response to PVT variations. Referring to FIG. 2, the falling skew between the first internal clock signal CLKB and the second internal clock signal CLK1 has a variation range from about +20 picoseconds (ps) to about −16 picoseconds in response to the PVT variations.
FIG. 3 illustrates a rising skew, between the first internal clock signal CLKB and the second internal clock signal CLK1 output from the conventional phase splitter 101 illustrated in FIG. 1, in response to PVT variations. Referring to FIG. 3, the rising skew between the first internal clock signal CLKB and the second internal clock signal CLK1 has a variation range from about +14 picoseconds to about −12 picoseconds in response to the PVT variations.
In the conventional phase splitter 101, as described above, the skew is generated between the first internal clock signal CLKB and the second internal clock signal CLK1 because the number of inverters in the first path X is greater than the number of inverters in the second path Y. Furthermore, the falling skew and the rising skew between the first internal clock signal CLKB and the second internal clock signal CLK1 have very large variation ranges. These variation ranges may become larger due to changes in PVT.
Large variations in the falling skew and rising skew between the first internal clock signal CLKB and the second internal clock signal CLK1 may cause error in data output from a semiconductor memory device (not shown) operating in synchronization with the first internal clock signal CLKB and the second internal clock signal CLK1. To prevent this, the skew between the first internal clock signal CLKB and the second internal clock signal CLK1 should be reduced.